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Category: AVR

Avr

Debugging Days

Last night we spend atleast 3 hours to track down a little bug in the cpu fuse settings. After running first tests on the hardware we got debug uart and some basic sreg addressing working.

Then we started to implement a sram read/write round trip. We found out that we read for all sram cells the same value as the last value which was written. So we stepped through the schematics and traced all IO lines and logic involved in the sram addressing process. First we analysed the sreg setup and the address counters. Then we checked the busdriver and the sram multiplexer. But this looked all out. Finally we found the problm that the WR line from the AVR to the sram is not pulled high when set in software.

So we looked for shortcircuits but didn’t find anything. Last guess was the mcu is broken, but finally we found out that we had a false fuse setting. So our IO pin was configured to passthru the clock signal on that pin. Fixed that and so basic sram read/write is working.

Tonite we gonna test bulk transfer. Hopefully this time we don’t have so nasty bugs.

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Dev Cart Block Diagramm

These two pictures show the different functional blocks of the prototype design. On the top side you have the MCU and next to it the connector for In-System-Programming and the MMC/SD daughter board. The yellow block marks the usb hardware for emulated software-usb on the mcu, the green block is the ram section. The orange block on top, right under the cart edge connector marks the bus transceivers to connect or disconnect the snes to the ram interface. The blue block overlays the transceiver for data access to the ram from the mcu side. The logic gates are for lo-/hiram switching and to disable write access to the ram section from the snes side.

On the bottom side you have a socket for the cic-lockout chip and the rest of the bus transceivers to connect or disconnect the snes. In the lower half you have shift registers to preset a certain adress to the adress counters. These counters are connected to the ram via bus transceivers, so you can access large memory with only a few io-pins on the mcu side. The red block is a demultiplexer to distribute the 22bit adresses to the 19 bit adresses of the ram ics.

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The Eagle has landed – Assembled and powered up

Finally assembled and the pcb powers up. So iam posting a few more details photos.
The boards powers up and the FTDI can be accessed via usb. So tomorrow i gonna meet with max and we will port the old firmware from the mega16 to the mega644. Tomorrow we might have simple usb based uploader working.

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The Eagle has landed

This monday morning the long awaited first prototype PCB arrived from pcb-pool. We had a little UPS problem on friday, so we had to wait till monday to get the PCB. Max just started to solder all the chips, looking forward to get a working usb uploader firmware running till the next weekend.

I think the PCB looks really good and iam looking forward to power it up soon…

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The PCB is coming down

Got an mail from pcb-pool.de, our PCB is nearly done and will arrive this week. So the first prototype will be assembled over the weekend. Keep fingers crossed that everything is working as planed.

Quick Featuers list

  • ATMega 644
  • Software USB
  • FTDI USB Debug port
  • 4MB SRAM
  • LO/HI Rom Switch
  • SD Card Daughter Board
  • AVR Cart IRQ Trigger
  • AVR WR sniffer

Things not happping with this version

  • Save Game support by design
  • DSP Support
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