Yeah, its working. Have been playing Super Mario Word last night. Did a few tests with different roms. Mainly Lorom, type 0 without save game ram. Was able to run games up to 16bmit. Couldn’t find any 32mbit type 0 games to test the complete ram area. Anyways its working finally. What de did? Resolder the cart connector and cleaned the contacts 🙂
And some pictures of the OR gate hack:
Now its time to work on the software side. Stay tuned.
I did some more debugging over the weekend. The thing to investigate was why roms crash or hang when music starts. That was the last suspicion we had on thursday.
So mukunda from #snesdev helped me and made a few test roms to investigate the problem with the SPC. First we started with a simple test to find out that during the SPC boot the system stalls.
So it was verified, that music triggers the problem.
I learned that the system needs to read back $2140 and $2141 to get the SPC status. So where software will wait for $AABB in that registers. I suggested to mukunda to add verbose debug printing on the display to see the register status. Also he added color flashing of the background so see if the snes crashes or just idles on the register poll.
So it came out that the register always reads $2121, which is an openbus. Made a video from that tests:
So i suspected that there is something wrong with the CART/CS line, because it looks like the rom doesn’t
Background to this is that MMIO access of the register $2140/2141 make the address appear on the A bus. RD will go low and CS will go high for deselecting the rom. This should activate the SPC on the A bus.
So i made a little logic analyzer session with the prototype board to verify this. The outcome looked quite ok.
Next day Max joined me debugging and i explained him that we have a conflict on the A bus during MMIO. Going thru the schematics we figured out that the only weak spot could be the busdriver which forwards the CART IO line and switches the ram address and data bus to the SNES A bus.
So Max added another OR gate to get better control over the CS line. What we needed was this:
CS: Cart ( low active )
EN: SNES enable from avr
G: Busdriver enable
CS EN G
1 1 1
0 1 1
1 0 1
0 0 0
Since i didn’t had anything better than an 74LS00 at home, we did it with 3 AND gates.
And this did the trick. Now we were able to boot roms which used the SPC. So we think the problem was that the budsriver was soaking up too much voltage, when the SNES was pulling CS hi the SPC didn’t got triggered.
After running a few games, we found that that now he have random crashes somewhere else 🙁
Have to investigate this right now…
Last night i had a long debug session with Max and we tried to track down the problem with the prototype board.The problem is that some homebrew roms are runinng fine, but most commerical games don’t even start. I can start up the game “Mr. Do”, but it hangs directly at the first intro screen.
So we investigated this. We went thru all logic step involving setting up our hardware. Double checked all IO Ports and Input/Output behaviour. Re-wrote all our setup routines and switching functions, like Lo/Hi rom switching and bus driver switching. Did memory pattern checking from the AVR and the SNES side.
Added extra delays to critical area and double checked all IO line on the board.
And guess what. Still the same problem. Nearly everything crashes.
So here are the news, we figured out as soon as a rom start music its crashes. So all homebrew stuff without SPC stuff works fine. But can’t get any homebrew or commerical stuff running thats uses sound.
I don’t have any deep knowledge about the sound sub system of the SNES. I only know its co-processor called SPC, it gets his IPL from the SNES and it has to be setup with code/music via a dedicated 8bit data port. So i assume there is no direct rom access from the SPC to the cartridge. So why is his a problem on our prototype board. We never had this kind of problem with the proof of concept board.
Last options we are thinking are: We either have a problem with the SRAM timings, since we use faster SRAM on the prototype board. The proof of concept board used 70ns SRAMs, now we are running 50ns. Or the capacitors on the SRAMs are to small. I would appreciate if anybody reading this have experienced same problems or knows what causing this problem could leave me a comment or contact me on #snesdev.
The last 2 nights i spend some time debugging the firmware of the prototype board. I added CRC checks for the sram areas and each uploaded bank. Hence i can push roms to the sram and verify it at runtime on both sides. So i can see if there are any transfer errors. Iam not using any CRC checks on USB layer, because the VUSB lib only supports this for 18MHz driven mcpus and we use 20MHz. This why i have to do it by ‘hand’ later after a block/bank is upoaded.
Also i switched the SRAM addressing mode to the faster counter based version. This boosted the upload speed by a great magnitude. I guess there is more room for optimization, but right now its quite fast to upload a rom. Like 2 seconds for a 32kb LOROM bank. So just a few seconds for a 4mbit game.
I know that USB could do much faster, but there are limits to the USB lib we are using. The client side allows only transfer up to 254 for each call. Minus the protocol overhead. Also the host side runs in user mode and can’t be compared to a kernel module performance. USB Transfer is realized thru callback in the firmware. Right now an 128 Bytes data transfer is splitted into 16 times 8 bytes payload callbacks. So i got a huge accumulated function overhead with this. Either i have to optimize this callback behavior or do it in ASM to squeeze out some cycles.
There a little downside right now. I can’t get commerical roms working. Iam able to upload and run homebrew stuff, but games doesn’t seem to boot. Sometime i have weird crashes in homebrew stuff.
I can assume that our attached CRC chip is working, because i made it into the start screen of Mr.Do, but Super Mario World doesn’t even show up the Nintendo start logo.
I guess there is something wrong with the our HI/LOROM or WR Enable switching logic. Have to investigate this….
Last night we spend atleast 3 hours to track down a little bug in the cpu fuse settings. After running first tests on the hardware we got debug uart and some basic sreg addressing working.
Then we started to implement a sram read/write round trip. We found out that we read for all sram cells the same value as the last value which was written. So we stepped through the schematics and traced all IO lines and logic involved in the sram addressing process. First we analysed the sreg setup and the address counters. Then we checked the busdriver and the sram multiplexer. But this looked all out. Finally we found the problm that the WR line from the AVR to the sram is not pulled high when set in software.
So we looked for shortcircuits but didn’t find anything. Last guess was the mcu is broken, but finally we found out that we had a false fuse setting. So our IO pin was configured to passthru the clock signal on that pin. Fixed that and so basic sram read/write is working.
Tonite we gonna test bulk transfer. Hopefully this time we don’t have so nasty bugs.